Semiconductor integrated circuit technology is developing rapidly and one aspect of this is that modern integrated circuit devices are being designed to operate from system supply voltages which are beckoning lower. For example, many of todays integrated circuit devices operate from a 5 volt supply, whilst newer integrated circuit devices operate from a 3.3 volt supply. Some state of the art devices operate from even lower supplies of 2.5 volts or less. Accordingly, mixed voltage systems have become necessary which require "overvoltage" tolerant interfaces which allow devices which operate from a lower supply voltage to interface with other devices which operate at a higher supply voltage. As an example, FIG. 1 shows a bus 1 connected to a number of integrated circuits 2. Each device includes an i/o interface comprising an input buffer 3 and an output buffer 4 connected to the bus 1 via a pad 5. Some of the devices 2 operate from a 5 volt supply voltage whilst others operate from a lower supply voltage of 3.3 volts. Accordingly, the bus 1 has a low logic level of around 0 volts but a high logic level of between 3.3 and 5 volts, depending on which device is active. Only one of the devices 2 can drive the bus at any one time whilst the others are held in a high impedance state to ensure that they do not alter the logic level appearing on the bus 1. It is important that any device 2 which operates at the lower voltage level must be able to connect to the bus 1, even when the bus is at the higher voltage level.
FIG. 2 shows an input buffer 3 which includes a conventional bus hold circuit 6. A bus hold circuit is designed to prevent a bus from floating to an undefined state when all of the devices connected to the bus are in a high impedance state. Without this, the input buffers of devices connected to the bus could produce false transitions and may also dissipate unacceptably high currents. The bus hold circuit 6 comprises a first CMOS inverter 7 connected in a feedback path around a second CMOS inverter 8. An input to the second CMOS inverter 8 is connected to an input pad 5. The first CMOS inverter 7 includes a PMOS transistor connected in series with an NMOS transistor, the source of the PMOS transistor being connected to a 3.3 volt supply (Vcc). In use, the input pad 5 is driven by a bus and therefore the voltage which appears at the pad 5 will correspond to whatever voltage level is on the bus. The bus hold circuit 6 is designed to allow the bus to drive the input to the second inverter 8 high or low. The bus hold circuit 6 will hold the input at whatever logic level the bus was at until the pad 5 is next driven low or high by the bus so that the bus state does not become undefined. To sustain a bus hold, the first CMOS inverter 7 must be connected to the pad 5. If 5 volts is applied to a bus hold circuit operating from a 3.3 volt supply voltage (Vcc), a parasitic N-well diode (not shown) associated with the PMOS transistor of the first CMOS inverter 7 becomes forward biassed and injects current into Vcc. The N-well diode turns on when the pad voltage rises above Vcc. Furthermore, the PMOS transistor turns on as its drain voltage rises above Vcc causing an additional drain-source current to flow. In each case, the effect of the overvoltage on pad 5 is to source current from a device driving the pad into Vcc. This will lead to a low transition on the bus and may even damage the device driving the bus to 5 volts. The effect is even worse during live insertion of a device 2 onto the bus 1 since there is no voltage supply to the device when it is first connected to the bus. Accordingly, the bus hold circuit 6 shown in FIG. 2 cannot be connected to a mixed bus of the type shown in FIG. 1 because the PMOS transistor components will not function properly. If an NMOS transistor is used instead of a PMOS transistor in inverter 7 the problem of current injection into the 3.3 volt apply under overvoltage conditions could be avoided. However, an NMOS transistor connected to Vcc does produce a sufficiently high voltage level on its output due to its threshold voltage and backbody effects. An NMOS transistor could be used if its gate voltage is raised to a voltage higher than the on-chip supply Vcc by an amount which would overcome the threshold and backbody effects. However, the circuitry required to produce voltages higher than the on-chip supply tend to consume a great deal of power and are not suitable for use with a device designed for low power applications. Accordingly, use of PMOS pull-up transistors is preferred since when pulling high the drain voltage can reach the same level as the source voltage.
FIG. 3 shows a simplified example of a conventional output buffer 9 which includes a number of CMOS inverters which use PMOS transistors powered by a 3.3 volt supply (Vcc). Again, should the pad 5 be driven to a voltage above Vcc by a bus 1, the parasitic N-well diode (not shown) associated with the PMOS transistor connected to the pad 5 becomes forward biassed and so turn on, injecting current into its N-well. Also, this PMOS transistor turns on as the drain voltage rises above Vcc. In each case, the effect is to source current into the voltage supply (Vcc). Accordingly, the output buffer 9 shown in FIG. 3 cannot be connected to a mixed bus 1 of the type shown in FIG. 1 because the PMOS transistor components will not function properly.